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low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer ics8545 idt? / ics? lvds fanout buffer 1 i cs8545BG rev. d october 28, 2008 description the ics8545 is a low skew, high performance 1-to-4 lvcmos/lvttl-to-lvds clock fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. utilizing low voltage differential signaling (lvds) the ics8545 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100 ? . the ics8545 accepts a lvcmos/lvttl input leve l and translates it to 3.3v lvds output levels. guaranteed output and part-to-part skew characteristics make the ics8545 ideal for those applications demanding well defined performance and repeatability. features ? four differential lvds output pairs ? two lvcmos/lvttl clock inputs to support redundant or selectable frequency fanout applications ? maximum output frequency: 650mhz ? translates lvcmos/lvttl input signals to lvds levels ? output skew: 40ps (maximum) ? part-to-part skew: 500ps (maximum) ? propagation delay: 3.6ns (maximum) ? additive phase jitter, rms: 0.13ps (typical) ? full 3.3vsupply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s ics8545 20-lead tssop 6.5mm x 4.4mm x 0.925 mm package body g package top view pin assignment block diagram 0 1 nd q le 0 1 q0 q0 q1 q1 q2 q2 q3 q3 l k_en clk1 clk2 k _sel oe pulldown pulldown pulldown pullup pullup 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd oe nc clk2 nc clk1 clk_sel clk_en gnd v dd q0 q0 v dd q1 q1 q2 q2 gnd q3 q3
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 2 ics8545BG rev. d october 28, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 9, 13 gnd power power supply ground. 2 clk_en input pullup synchronizing clock enable. when high, clock outputs follows clock input. when low, q outputs are forced low, q outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when high, selects clk2 input. when low, selects clk1 input. lvcmos / lvttl interface levels. 4 clk1 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 5, 7 nc unused no connect. 6 clk2 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 8 oe input pullup output enable. controls enabling and disabling of outputs q0/q0 through q3/q3 . lvcmos/lvttl interface levels. 10, 18 v dd power positive supply pins. 11, 12 q3 , q3 output differential output pair. lvds interface levels. 14, 15 q2 , q2 output differential output pair. lvds interface levels. 16, 17 q1 , q1 output differential output pair. lvds interface levels. 19, 20 q0 , q0 output differential output pair. lvds interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 3 ics8545BG rev. d october 28, 2008 function tables table 3a. control input function table after clk_en switches, the clock outputs are disabled or enab led following a rising and falling input clock edge as shown in fi gure 1. in the active mode, the state of the outputs are a functi on of the clk1 and clk2 inputs as described in table 3b. figure 1. clk_en timing diagram table 3b. clock input function table inputs outputs oe clk_en clk_sel selected source q0:q3 q0 :q3 0 x x hi-z hi-z 100clk1lowhigh 101clk2lowhigh 1 1 0 clk1 active active 1 1 1 clk2 active active inputs outputs clk1 or clk2 q0:q3 q0 :q3 0lowhigh 1highlow enabled disabled clk1, clk2 clk_en q0 :q3 q0:q3
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 4 ics8545BG rev. d october 28, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma package thermal impedance, ja 73.2 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 50 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage clk1, clk2 -0.3 1.3 v oe, clk_en, clk_sel -0.3 0.8 v i ih input high current clk1, clk2, clk_sel v dd = v in = 3.465v 150 a oe, clk_en v dd = v in = 3.465v 5a i il input low current clk1, clk2, clk_sel v dd = 3.465v, v in = 0v -5 a oe, clk_en v dd = 3.465v, v in = 0v -150 a
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 5 ics8545BG rev. d october 28, 2008 table 4c. lvds dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c all parameters measured at f max unless noted otherwise. note 1: measured from v dd /2 of the input to the differential output crossing point. note 2: defined as skew between outputs at the sa me supply voltage and with equal load conditions. measured at v dd /2 of the input to the differential output crossing point. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the output s are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units v od differential output voltage 200 280 360 mv ? v od v od magnitude change 40 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 5 25 mv i oz high impedance leakage -10 1 +10 a i off power off leakage -20 1 +20 a i osd differential output short circuit current -3.5 -5 ma i os output short circuit current -3.5 -5 ma v oh output voltage high 1.34 1.6 v v ol output voltage low 0.9 1.06 v parameter symbol test conditio ns minimum typical maximum units f max output frequency 650 mhz t pd propagation delay; note 1 ? 650mhz 1.4 3.6 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 156.25mhz, integration range: 12khz ? 20mhz 0.13 ps t sk(o) output skew; note 2, 4 40 ps t sk(pp) part-to-part skew; note 3, 4 500 ps t r / t f output rise/fall time 20% to 80% @ 50mhz 200 400 600 ps odc output duty cycle 45 50 55 %
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 6 ics8545BG rev. d october 28, 2008 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. ssb phase noise dbc/hz offset frequency (hz)
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 7 ics8545BG rev. d october 28, 2008 parameter measureme nt information 3.3v lvds output load ac test circuit part-to-part skew output duty cycle/pulse width/period differential output level output skew propagation delay scope qx nqx lvds 3.3v5% power supply +? float gnd - v dd t sk(pp) part 1 part 1 qx qx qy qy t pw t period t pw t period odc = x 100% q0 :q3 q0:q3 - v os cross points v od v dd gnd q0 :q3 q0:q3 t sk(o) qx qx qy qy tp lh q0 :q3 q0:q3 clk1, clk2
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 8 ics8545BG rev. d october 28, 2008 parameter measurement in formation, continued output rise/fall time offset voltage setup high impedance leakage current setup power off leakage setup differential output voltage setup differential output short circuit setup clock outputs 20% 80% 80% 20% t r t f v od out out lvds dc input ? ? ? v os / ? v os v dd out out lvds dc inpu t ? ? 3.3v5% power supply float gnd + _ i oz i oz lvds ? i off v dd ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? i osd v dd
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 9 ics8545BG rev. d october 28, 2008 parameter measurement in formation, continued output short circuit current setup application information recommendations for unused input and output pins inputs: clk inputs for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. out lvds dc input ? i os ? i osb v dd out
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 10 ics8545BG rev. d october 28, 2008 3.3v lvds driver termination a general lvds interface is shown in figure 2. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 2. typical lvds driver termination 3.3v lvds driver r1 100 ? ? + 3.3v 50 ? 50 ? 100 ? differential transmission line
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 11 ics8545BG rev. d october 28, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics8545. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8545 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * i dd_max = 3.465v * 50ma = 173.25mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the ap propriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer bo ard, the appropriate value is 66.6c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.173w * 66.6c/w = 81.5c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resitance ja for 20 lead tssop, forced convection ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 12 ics8545BG rev. d october 28, 2008 reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics8545 is: 644 package outline and package dimension package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 13 ics8545BG rev. d october 28, 2008 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8545BG ics8545BG 20 lead tssop tube 0 c to 70 c 8545BGt ics8545BG 20 lead tssop 2500 tape & reel 0 c to 70 c 8545BGlf ics8545BGlf ?lead-free? 20 lead tssop tube 0 c to 70 c 8545BGlft ics8545BGlf ?lead-free? 20 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt rese rves the right to change any ci rcuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devi ces or critical medical instruments.
ics8545 low skew, 1-to-4, lvcmos/lvttl-to-lvds fanout buffer idt? / ics? lvds fanout buffer 14 ics8545BG rev. d october 28, 2008 revision history sheet rev table page description of change date a t4c 4 in the v ol row, 1.06 has been moved to the typical column from the maximum column. 9/21/01 a 3 revised figure 1, clk_en timing diagram. 10/17/01 a 3 revised figure 1, clk_en timing diagram. 11/2/01 b 4c 1 4 8-9 features - deleted bullet ""designed to meet or exceed the requirements of ansi tia/eia-644"". lvds table - changed vod typical value from 350mv to 280mv. updated lvds diagrams. 9/19/02 c t2 2 4 8 pin characteristics - changed c in 4pf max. to 4pf typical. absolute maximum ratings - changed output rating. added lvds driver termination section. updated format throughout data sheet. 1/5/04 c t8 1 8 11 features section - added lead-free bullet. added recommendations for unused input and output pins. ordering information table - added lead-free part number, marking and note. 1/17/06 d t5 1 5 6 11 features section - added additive phase jitter bullet. ac characteristics table - added additive phase jitter spec. added additive phase jitter plot. added power considerations section. 5/31/07
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